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M-993
Region 1 MF Tone Generator
Features * Generates standard CCITT R1 MF tones * Digital input control * Linear (analog) output * Power output capable of driving standard line * 14-pin DIP * Single 5-Volt supply * Inexpensive 3.58 MHz time base Applications * Telephone systems * Test equipment Description The M-993 is a monolithic CMOS integrated circuit designed to generate multifrequency (MF) tone pairs for use in trunk signaling. The tones generated conform to CCITT R1 signal recommendations and to AT&T MF standards. The M-993 permits design engineers to implement a highly accurate MF sender with a minimum of space, power, and added components. The accuracy of the tone frequencies is assured through use of an easily obtained 3.58 MHz color burst crystal or an external 3.58 MHz clock source.
Ordering Information Part # M-993 Description 14-pin plastic DIP
Pin Diagram
Block Diagram
DS-M993-R1
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M-993
Absolute Maximum Ratings
Storage Temperature Operating Ambient Temperature VDD Any Input Voltage -55 to 125C -25 to 70C 7.0V VSS - 0.6 to VDD + 0.6V Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and effect its reliability.
Note: 1. Exceeding these ratings may permanently damage the M-993.
Specifications
Parameter VDD Current Drain, IDD VREF PIN: Voltage Internal Resistance from VREF to VDD, VSS Frequency Deviation External CLock: (XOUT open) VIL VIH Duty Cycle XIN, XOUT Loading: Capacitance Resistance Frequency Deviation Level Distorting Components Idle OUTDRIVE Envelope Rise Time DX, CE Pins: VIL VIH Mute Pins: VOL (ISINK = -100 A) VOH (ISOURCE = 100 A) Data Setup (tDSRT) Data Hold (tDH) Chip Enable Fall (tPL) Tone On Delay (tTO) Tone Off Delay (tTD) Mute Delay from Outdrive (tMO) Min 4.75 48% of VDD 3.25 -0.01 0 VDD- 0.2 40 20 -1.5 110 -35 2.5 VDD- 1.5 200 10 5 5 Typ 2.0/4.0 Max 5.25 52% of VDD 6.75 +0.01 0.2 VDD 60 10 1.5 180 -60 4 0.5 1.5 90 200 Units V mA % k % V V % pF M % mV dB dBm ms V V V V ns ns ns ms ms ns Notes 1 8 7 9 2 2, 3 4 5 6 10 -
Power Supply and Reference
Oscillator
Tone Output
Control
Timing
Unless otherwise noted, VDD - VSS = 5 VDC, Ta - 25 C Notes: 1. All DC voltages are referenced to VSS. 2. Vrms per tone, 540W load. 3. Any one frequency relative to the lowest level output tone (f<4000 Hz). 4. 0 dBm = 0.775 Vrms. 5. To 90% maximum amplitude.
6. For all supply voltages in the operating range. 7. At XOUT pin as compared to 3.579545 MHz. 8. OUTDRIVE with load >5 KW/OUTDRIVE with 540W load. 9. Crystal oscillator active. 10. Measured 90% to 10%.
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M-993
Pin Function
Pin CE D0 - D3 D4-D5 MUTE OUTDRIVE VDD VREF VSS XIN XOUT Function Latches data and enables output (active low input). Data input pins. (See Data/Tone Selection.) Leave open. Output indicates that a signal is being generated at OUTDRIVE. Linear buffered tone output. Most positive power supply input pin. Internally generated mid-power supply voltage (output). Most negative power supply input pin. Crystal oscillator or digital clock input. Crystal oscillator output.
Data/Tone Selection
D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D0 Frequency (Hz) 1 2 0 1100 1700 1 700 900 0 700 1100 1 900 1100 0 700 1300 1 900 1300 0 1100 1300 1 700 1500 0 900 1500 1 1100 1500 0 1300 1500 1 1500 1700 0 900 1700 1 1300 1700 0 700 1700 Use Key Pulse (KP) Digit 1 Digit 2 Digit 3 Digit 4 Digit 5 Digit 6 Digit 7 Digit 8 Digit 9 Digit 0 ST ST1 ST2 ST3
Power-On Reset Circuit
A typical control sequence for the M-993 is: (1) set data lines Selection for data settings for a particular tone pair output).to desired frequency selection, (2) wait for data lines to settle, (3) drive the chip enable (CE) low, (4) maintain CE low for desired tone duration (Note: data lines may be changed after data hold time), and (5) return CE to a logic high. In a bus-oriented system, noise on the data lines may propagate through the device and appear at the output. To safeguard against this, use an external latch to clock the data into the device. In addition, it is good
practice to bypass the VREF pin to ground with a small capacitor (~0.01mF) to reduce power supply noise. The designer should be aware of device timing requirements and design accordingly. Beware of hardwiring the data input pins for dedicated tone generation. An RC network like that shown in Power-On Reset Circuit should be used to momentarily reset the device immediately following a power-up to ensure reliable operation.
Rev. 1
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M-993
Timing Diagram
Expanded Timing Diagram
Typical Application
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M-993
Mechanical Dimensions
Tolerances Inches A A1 b b2 C D E E1 e ec L Min .015 .014 .045 .008 .735 .300 .240 .100 BSC 0 .115 15 .150 Max .210 .022 .070 .014 .775 .325 .280 Metric (mm) Min Max 5.33 .38 .36 .56 1.1 1.8 .20 .36 18.7 19.7 7.6 8.3 6.1 7.1 2.54 BSC 0 15 2.9 4.1
Dimensions mm (inches)
Rev. 1
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Worldwide Sales Offices
CLARE LOCATIONS
Clare Headquarters 78 Cherry Hill Drive Beverly, MA 01915 Tel: 1-978-524-6700 Fax: 1-978-524-4900 Toll Free: 1-800-27-CLARE Clare Switch Division 4315 N. Earth City Expressway Earth City, MO 63045 Tel: 1-314-770-1832 Fax: 1-314-770-1812 Clare Micronix Division 145 Columbia Aliso Viejo, CA 92656-1490 Tel: 1-949-831-4622 Fax: 1-949-831-4628
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Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-M-993-R1 (c)Copyright 2001, Clare, Inc. All rights reserved. Printed in USA. 7/18/01

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